듀얼 주파수 체배기를 이용한 전치왜곡 선형화기 설계 및 제작

• 영문명: Design and Implementaion of a Predistortion Linearizer Using Dual Frequency Multiplier
• 발행기관: 개인저작물
• 저자명: 홍의석, 배상균(Bae Sang_gyun) 우민근, 김용환
• 간행물 정보: 『개인저작물 - 공학』제29권 제2호, 1~4쪽, 전체 4쪽
• 주제분류: 공학 > 개인저작물
• 파일형태: PDF
• 발행일자: 2004.07.01

영문 초록

In this thesis,a predistortion linearizer was designed and fabricated with a dual frequency multiplier empolying harmonic injection method for high power amplifier in CDMA repeater. To supress the spectral regrowth in the adjacent channels effectively, the odd order intermodulation distortions should be cancelled. For the purpose, the predistorter, which can cancel the 3rd and 5th intermodulation distortions independently, has been implemented. The predistortion linearizer used a dual frequency multiplier to minimize size and DC current. The implemented predistorter linearized the RF power amplifier with average power 40dBm at 870~880MHz band. The predistortion linearizer was improved by 22dB IMD(intermodulation distortion) at 2-tone signals(37dBm/tone) and 6.8dB ACPR(Adjacent Channel Power Ratio) at 1FA CDMA source signals from 1.98MHz offset. By applying this predistorter to amplifier, PAE(Power Added Efficiency) performance of power amplifier was improved by 7% under same ACPR specification.

목차

I. 서론

Ⅱ. 듀얼 주파수 체배기를 이용한 전치왜곡 선형화기

Ⅲ. 전치왝곡 선형화기 설계

Ⅳ. 전치왜곡 선형화기 측정

V. 결론

참고문헌

초록