A Method for Reducing the Number of Metal Layers for Embedded LSI Package

• 발행기관: 한국마이크로전자및패키징학회
• 저자명: Daisuke Ohshima Kentaro Mori Yoshiki Nakashima Katsumi Kikuchi Shintaro Yamamichi
• 간행물 정보: 『마이크로전자 및 패키징학회지』제17권 제4호, 27~33쪽, 전체 7쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2010.12.31

영문 초록

We have successfully demonstrated a high-pin-count and thin embedded-LSI package to realize next generation's mobile terminals. The following three design key points were applied: (i) Using Cu posts, (ii) Using the coreless structure, (iii) Using a Cu plate as the ground plane. In order to quantitatively determine the contribution of the three points, the five-stage process for reducing the number of metal layers is described by means of the electrical simulation. The point-(i) and (ii) are effective from the viewpoint of the power integrity (PI); that is, these points play important roles in reducing the number of metal layers, and especially the point-(ii) contributes at least twice as the point-(i). The point-(iii) is not effective in the PI, but has a few effects on the signal integrity (SI). For reducing the number of metal layers, we should, at first, pay attention whether the PI characteristics fulfill the specification, and then we should confirm the SI characteristics.

목차

1. Introduction

2. Package Structures

3. Three Key Points of the Package Designs

4. A method for reducing the number of metal layers

4. Evaluation Method

5. Results and Discussion

6. Conclusions

Acknowledgments

References

키워드

Embedded-LSI packaging power integrity characteristics signal integrity characteristics next generation mobile terminal