- 영문명
- 발행기관
- 한국마이크로전자및패키징학회
- 저자명
- R. Crisp Crisp,R.
- 간행물 정보
- 『마이크로전자 및 패키징학회지』제19권 제4호, 45~50쪽, 전체 6쪽
- 주제분류
- 공학 > 산업공학
- 파일형태
- 발행일자
- 2012.12.31

국문 초록
영문 초록
A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the centerbonded devices (DDR3, DDR4 and LPDDR3 ×16 die) and for the face up wirebonded ×32 LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.
목차
1. Introduction
2. Ball Assignment Design
3. Test Hardware Consolidation
4. System Design
5. Feasibility Study
6. Reference Design: SDP Memory With HDI(12 layer: 3-6-3) TYPE-4 PCB
7. Details: Comparison of Memory Footprint Layouts
8. Features and Versatility of Ballout
9. Conclusion
References
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