슈퍼 칩 구현을 위한 헤테로집적화 기술

• 영문명: Ultimate Heterogeneous Integration Technology for Super-Chip
• 발행기관: 한국마이크로전자및패키징학회
• 저자명: 이강욱
• 간행물 정보: 『마이크로전자 및 패키징학회지』제17권 제4호, 1~9쪽, 전체 9쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2010.12.31

영문 초록

Three-dimensional (3-D) integration is an emerging technology, which vertically stacks and interconnects multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip to form highly integrated micro-nano systems. Since CMOS device scaling has stalled, 3D integration technology allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. The potential benefits of 3D integration can vary depending on approach; increased multifunctionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. It is expected that the semiconductor industry's paradiam will be shift to a new industry-fusing technology era that will offer tremendous global opportunities for expanded use of 3D based technologies in highly integrated systems. Anticipated applications start with memory, handheld devices, and high-performance computers and extend to high-density multifunctional heterogeneous integration of IT-NT-BT systems. This paper attempts to introduce new 3D integration technologies of the chip self-assembling stacking and 3D heterogeneous opto-electronics integration for realizng the super-chip.

목차

1. 서론

2. 삼차원집적화기술의 현황과 과제

3. Super-Chip 기술

4. 요약

감사의 글

참고문헌