A Study of Wire Sweep During Encapsulation of Semiconductor Chips

• 영문명: A Study of Wire Sweep During Encapsulation of Semiconductor Chips
• 발행기관: 한국마이크로전자및패키징학회
• 저자명: Han, Se-Jin Huh, Yong-Jeong
• 간행물 정보: 『마이크로전자 및 패키징학회지』제7권 제4호, 17~22쪽, 전체 6쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2000.12.31

영문 초록

In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.

목차

1. Introduction

2. Wire Sweep Analysis

3. Conclusion

References