5 nm 급 반도체 배선 공정 기술 개발

• 영문명: Development of Interconnect Process Technology for 5 nm Technology Nodes
• 발행기관: 한국마이크로전자및패키징학회
• 저자명: 최은미 표성규
• 간행물 정보: 『마이크로전자 및 패키징학회지』제23권 제4호, 25~29쪽, 전체 5쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2016.12.31

영문 초록

The semiconductor industry has been developed mainly by micronization process due to many advantages of miniaturization of devices. Mass production of semiconductors of 10 nm class has been started recently, and it is expected that the technology generation of 5 nm & 7 nm technology will come. However, excessive linewidth reduction affects physical limits and device reliability. To solve these problems, new process technology development and new concept devices are being studied. In this review, we introduce the next generation technology and introduce the advanced research for the new concept device.

목차

1. 서론

2. 5 nm 및 7 nm 급 반도체 배선 공정기술

3. 반도체 배선 공정 기술의 새로운 발전방향

4. 결론

References

키워드

5 nm & 7 nm technology 3D integration carbon semiconductor air gap Extreme ultraviolet