Implementation of a High Performance XOR-XNOR Circuit

• 발행기관: 한국전자통신학회
• 저자명: 김정범(Jeong-Beom Kim)
• 간행물 정보: 『한국전자통신학회 논문지』제17권 제2호, 351~356쪽, 전체 6쪽
• 주제분류: 공학 > 전자/정보통신공학
• 파일형태: PDF
• 발행일자: 2022.04.30

영문 초록

The parity function can be implemented with XOR (exclusive-OR) and XNOR (exclusive NOR) circuit. In this paper we propose a high performance XOR-XNOR circuit. The proposed circuitreduced the internal load capacitance on critical path and implemented with 8 transistors. The circuit produces a perfect output signals for all input combinations. Compared with the previous circuits, the proposed circuit presents the improved characteristics in average propagation delay time, power dissipation, power-delay product (PDP), and energy-delay-product (EDP). The proposed circuits are implemented with standard CMOS 0.18um technology. Computer simulations using SPICE show that the proposed circuit realizes the expected logic functions and achieves a reasonable performance.

목차

Ⅰ. Introduction

Ⅱ. Previous works

Ⅲ. Proposed circuits

Ⅳ. Simulation results

Ⅴ. Conclusion

키워드

Parity Function XOR-XNOR High-Performance Circuit Low-Power Circuit Energy-Efficient Circuit PDP EDP