수율향상을 위한 반도체 EDS공정에서의 불량유형 자동분류

• 영문명: Automatic Classification of Failure Patterns in Semiconductor EDS Test for Yield Improvement
• 발행기관: 한국시뮬레이션학회
• 저자명: 한영신(Young Shin Han) 이칠기(Chil Gee Lee)
• 간행물 정보: 『한국시뮬레이션학회 논문지』제14권 제1호, 1~8쪽, 전체 8쪽
• 주제분류: 공학 > 기타공학
• 파일형태: PDF
• 발행일자: 2005.03.30

영문 초록

In the semiconductor manufacturing, yield enhancement is an urgent issue. It is ideal to prevent all the failures. However, when a failure occurs, it is important to quickly specify the cause stage and take countermeasure. Reviewing wafer level and composite lot level yield patterns has always been an effective way of identifying yield inhibitors and driving process improvement. This process is very time consuming and as such generally occurs only when the overall yield of a device has dropped significantly enough to warrant investigation. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. The automatic method of failure pattern extraction from fail bit map provides reduced time to analysis and facilitates yield enhancement. This paper describes the techniques to automatically classifies a failure pattern using a fail bit map.

목차

1. 서론

2. EDS 공정 및 불량 분석

3. 웨이퍼 불량 유형 정의

4. 웨이퍼 불량 유형 분류를 위한 Suppor Vector Machine

5. 실험환경 및 결과

6. 결론

참고문헌

키워드

Semiconductor Manufacturing EDS Process Fail Bit Map Failure Pattern