웨이퍼 오류 패턴 인식 시뮬레이션

• 영문명: Wafer Fail Pattern Classification Simulation
• 발행기관: 한국시뮬레이션학회
• 저자명: 김상진(Kim Sang-Jin) 한영신(Young Shin Han) 이칠기(Chil-Gee Lee)
• 간행물 정보: 『한국시뮬레이션학회 논문지』제12권 제3호, 13~20쪽, 전체 8쪽
• 주제분류: 공학 > 기타공학
• 파일형태: PDF
• 발행일자: 2003.09.30

영문 초록

Semiconductor Manufacturing has emerged as one of the most important world industries. Even with the highly automated and precisely monitored facilities used to process the complex manufacturing steps in a near particle free environment, processing variations in wafer fabrication still exist. The causes of these variations may arise from equipment malfunctions, delicate and difficult processing steps, or human mistakes. In this paper, we could specify the cause stage and the cause equipment and take countermeasures at a speed by the conventional method, without depending on the experience and skills of the engineer.

목차

1. 서론

2. 시스템 설계

4 . 오류 패턴 인식 프로그램 구현

5. 결론 및 향후 방향

참고문헌

키워드

Wafer Pattern Matching Electrical Die Sorting Correlation