연산증폭기의 슬루율 개선을 위한 병렬 전류감산기 설계

• 영문명: A Design of Improvements Slew-Rate Operating Amplifier Parallel Current Subtracter
• 발행기관: 한국산업기술융합학회(구. 산업기술교육훈련학회)
• 저자명: 권용복(Yong-Bok Kueon)
• 간행물 정보: 『한국산업기술융합학회 학술대회 논문집』2010년 전반기 학술대회 논문집, 49~53쪽, 전체 5쪽
• 주제분류: 공학 > 산업공학
• 파일형태: PDF
• 발행일자: 2010.02.23

영문 초록

This paper presents the design of Improvements slew-rate operating amplifier parallel current subtracter. In the circuit designed for slew-rate programmability is based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience of timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 4.17V/db to 20V/db, power dissipation ranging from 7.67mW to 3.87mW, and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.

키워드

Operating Amplifier 연산증폭기 Slew-Rate 슬루율 Current Subtracter 전류감산기 Signal Processing 신호처리 Settling Time 정착시간