ESD

Steven H. Voldman 지음

Wiley 2009년 07월 01일 출간

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Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics.This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit methodology.Look inside for extensive coverage on:failure analysis tools, EOS and ESD failure sources and failure models of semiconductor technology, and how to use failure analysis to design more robust semiconductor components and systems;electro-thermal models and technologies; the state-of-the-art technologies discussed include CMOS, BiCMOS, silicon on insulator (SOI), bipolar technology, high voltage CMOS (HVCMOS), RF CMOS, smart power, gallium arsenide (GaAs), gallium nitride (GaN), magneto-resistive (MR) , giant magneto-resistors (GMR), tunneling magneto-resistor (TMR), devices; micro electro-mechanical (MEM) systems, and photo-masks and reticles;practical methods to use failure analysis for the understanding of ESD circuit operation, temperature analysis, power distribution, ground rule development, internal bus distribution, current path analysis, quality metrics, (connecting the theoretical to the practical analysis);the failure of each key element of a technology from passives, active elements to the circuit, sub-system to package, highlighted by case studies of the elements, circuits and system-on-chip (SOC) in today-s products.ESD: Failure Mechanisms and Models is a continuation of the author-s series of books on ESD protection. It is an essential reference and a useful insight in

목차

About the Author.Preface.Acknowledgments.1 Failure Analysis and ESD.1.1 Introduction.1.2 ESD Failure: How Do Micro-electronic Devices Fail?.1.3 Sensitivity of Semiconductor Components.1.4 How Do Semiconductor Chips Fail&~&~Are the Failures Random or Systematic?.1.5 Closing Comments and Summary.Problems.References.2 Failure Analysis Tools, Models, and Physics of Failure.2.1 FA Techniques for Evaluation of ESD Events.2.2 FA Tools.2.3 ESD Simulation: ESD Pulse Models.2.4 Electro-Thermal Physical Models.2.5 Statistical Models for ESD Prediction.2.6 Closing Comments and Summary.Problems.References.3 CMOS Failure Mechanisms.3.1 Tables of CMOS ESD Failure Mechanisms.3.2 LOCOS Isolation-Defined CMOS.3.3 Shallow Trench Isolation (STI).3.4 Polysilicon-Defined Devices.3.5 Lateral Diode with Block Mask.3.6 MOSFETs.3.7 Resistors.3.8 Interconnects: Wires, Vias, and Contacts.3.9 ESD Failure in CMOS Nanostructures.3.10 Closing Comments and Summary.Problems.References.4 CMOS Circuits: Receivers and Off-Chip Drivers.4.1 Tables of CMOS Receiver and OCD ESD Failure Mechanisms.4.2 Receiver Circuits.4.3 Receivers Circuits with ESD Networks.4.4 Receiver Circuits with Half-Pass Transmission Gate.4.5 Receiver with Full-Pass Transmission Gate.4.6 Receiver, Half-Pass Transmission Gate, and Keeper Network.4.7 Receiver Circuit with Pseudo-zero VT Half-Pass Transmission Gate.4.8 Receiver with Zero VT Transmission Gate.4.9 Receiver Circuits with Bleed Transistors.4.10 Receiver Circuits with Test Functions.4.11 Receiver with Schmitt Trigger Feedback Networks.4.12 Off-Chip Drivers.4.13 Single NFET Pull-down OCD.4.14 Series Cascode MOSFETs.4.15 I/O Design Considerations and ESD Parasitic Failure Mechanisms.4.16 Closing Comments and Summary.Problems.References.5 CMOS Integration.

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저자(글) Steven H. Voldman

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Dr Steven H. Voldman received his B.S. in Engineering Science from the University of Buffalo (1979); M.S. EE (1981) and Electrical Engineer Degree (1982) from M.I.T; MS Engineering Physics (1986) and Ph.D EE (1991) from the University of Vermont under IBM's Resident Study Fellow Program. At M.I.T, he worked as a member of the M.I.T. Plasma Fusion Center, and the High Voltage Research Laboratory (HVRL). At IBM, as a reliability device engineer, his work include pioneering work in bipolar/ CMOS SRAM alpha particle and cosmic ray SER simulation, MOSFET gate-induced drain leakage (GIDL) mechanism, hot electron, epitaxy/well design, CMOS latchup, and ESD. Since 1986, he has been responsible for defining the IBM ESD/latchup strategy for CMOS, SOI, BiCMOS and RF CMOS and SiGe technologies. He has authored ESD and latchup publications in the area of MOSFET Scaling, device simulations, copper, low-k, MR heads, CMOS, SOI , Sage and SiGeC technology. Voldman served as SEMATECH ESD Working Group Chairman (1996-2000), ESD Association General Chairman and Board of Directors, International Reliability Physics (IRPS) ESD/Latchup Chairman, International Physical and Failure Analysis (IPFA) Symposium ESD Sub-Committee Chairman, ESD Association Standard Development Chairman on Transmission Line Pulse Testing, ESD Education Committee, and serves on the ISQED Committee, Taiwan ED Conference (T-ESDC) Technical Program Committee. Voldman has provided ESD lectures for universities (e.g. MIT Lecture Series, Taiwan National Chiao-Tung University, and Singapore Nanyang Technical University). He is a recipient of over 125 US patents, over 100 publications, and also provides talks on patenting, and invention. He has been featured in EE Times, Intellectual Property Law and Business and authored the first article on ESD phenomena for the October 2002 edition of Scientific American entitled Lightening Rods for Nanostructures, and Pour La Science, Le S

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